Irredundant sequential machines via optimal logic synthesis

optimal sequential logic synthesis can produce fallv testable nonscan finite state machines. Test generation algorithms can be used It is well known that optimal logic synthesis can ensure fully to remove all the redundancies in sequential machines resulting in testable combinational logic designs. In this paper. we show that fuily testable designs. However. in general. this method requires optimal sequential logic synthesis can produce irreduudant, fully exorbitant amounts of CPU time. The optimal synthesis procetestable finite state machines. Test generation algorithms can be dure presented in this paper represents a more efficient approach used to remove all the redundancies in sequential machines resultto achieve 100% testability. ing in a filly testable design. However. this method may require Synthesizing a sequential circuit from a State Transition Graph exorbitant amounts of CPU time. The optimal synthesis procedescription involves the steps of state minimization. state assigiidure presented in this paper represents a more efficient approach ment and logic optimization. Previous approaches (e.g. IS]) to to achieve 100VX* testability, producing fully and easily testable sequential circuits have enSynthesizing a sequential circuit from a State Transition Graph tailed the use of extra logic and constraints on state assignient description involves the steps of state minimization. state assignand logic optimization. In this paper. we show that 1007 testabilment and logic optimization. Previous approaches to producing itcan be ensured without the addition of extra logic and uthout fully and easily testable sequential circuits have involved the use constraitdon the state assignment and logic optimization. Thi, of extra logic and constraints on state assignment and logic optechnique can be used in conjunction with previous approache, timization. In this paper. we show that 100% testability can be to ensure that the s'ynthesized machine is easily testable. emiurd untout tMe addition of ertra logic and without constraint,, The finite automaton is represented by a State Transition on the state assignment and logic optimization. Unlike previous Graph. truth table or by an interconnection of gates and flipsynthesis approaches to ensuring fuUy testable machines. there is flops. The synthesized/re-synthesized logic-level implenjentation no area/performance penalty associated with this approach. This is guaranteed to be fully testable for all single stuck-at faults in thr technique can be used in conjunction with previous approaches combinational logic ulitlout access to thc nemnory elements. This to ensure that the synthesized nachine is easily testable. procedure representan alternative to a Scan Design methodolGiven a State Transition Graph specification. a logic-level auogy without the usual area and performance penalty associated tomaton that is fully testable for all single stuck-at faults in the with the latter method. combinational logic without access to the ,nemory elements is synBasic definitions and terminologies used are given in Section thesized. This procedure represents an alternative to a Scan De2. Various types of redundant faults in sequential circuits are design niethiodology without the usual area and performance penalty scribed in Section 3. In Section 4. we outline an optimal syithesis associated with the latter method, procedure of state minimization, state assignment and logic optimization that produces a highly testable Moore oi Mealy finite